ChipBench
Benchmarks
| Task Name | Dataset Name | SOTA Result | Trend | |
|---|---|---|---|---|
| Verilog generation | ChipBench-SC | Pass@136.7 | 14 | |
| Python reference-model generation | ChipBench-SC | Pass@143.3 | 10 | |
| Chip Placement and Routing | ChipBench wrapper43 | HPWL25,162,108 | 2 | |
| Chip Placement and Routing | ChipBench dft68 | HPWL5,161,437 | 2 | |
| Chip Placement and Routing | ChipBench ariane136 | HPWL9,497,615 | 2 | |
| Chip Placement and Routing | ChipBench ariane133 | HPWL5,838,502 | 2 |
Showing 6 of 6 rows