CVDP
Benchmarks
| Task Name | Dataset Name | SOTA Result | Trend | |
|---|---|---|---|---|
| Verilog generation | CVDP cid03 | Pass@1 Rate44 | 14 | |
| cid004: RTL – Code Modification | CVDP non-agentic 1.0 | Pass@120 | 13 | |
| Python reference-model generation | CVDP cid03 | Pass@143.3 | 10 | |
| cid016: Design Verification – Debugging / Bug Fixing | CVDP non-agentic 1.0 | Pass@122.86 | 10 | |
| cid007: RTL – Code Improvement (Linting / QoR) | CVDP non-agentic 1.0 | Pass@151.25 | 10 | |
| cid003: RTL – Natural Language Specification to Code | CVDP non-agentic 1.0 | Pass@130.77 | 10 | |
| cid002: RTL – Code Completion | CVDP non-agentic 1.0 | Pass@124.47 | 10 | |
| RTL Design Code Generation | CVDP cid03 | Function Accuracy39 | 8 | |
| RTL Design Code Generation | CVDP cid02 | Function Accuracy22.4 | 8 | |
| Code comprehension | CVDP (Code Verilog Design Problems) (test) | Total Passes106 | 8 |
Showing 10 of 10 rows