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RTLLM

Benchmarks

Task NameDataset NameSOTA ResultTrend
HDL generationRTLLM 2.0
Pass@169.17
40
Verilog Code GenerationRTLLM v1.1
Syn@5100
31
Verilog Code GenerationRTLLM v2
Pass@175.8
27
Verilog Code GenerationRTLLM v2.0
Pass@584.09
17
Verilog Code GenerationRTLLM v1
Pass@172.9
16
RTL code generationRtllm (test)
Pass@142
16
RTL generationRTLLM 50 cases (test)
Pass@10.42
16
RTL code generationRTLLM v2.0 (test)
Syntax Pass@176.2
16
RTL Design GenerationRTLLM v2.0
Delay (ns)0.07
15
RTL GenerationRTLLM v2
Pass@171.8
13
Verilog GenerationRTLLM v2
Pass@20090
12
Verilog GenerationRTLLM v2 (test)
Pass@168
11
Python reference-model generationRTLLM v2
Pass@177.3
10
Verilog Code GenerationRTLLM 2.0 (test)
Pass@174.45
10
RTL Design Code GenerationRTLLM v1.1
Syntax Accuracy92
9
Hardware GenerationRTLLM 50 problems
Compile Success Rate96
5
RTL GenerationRTLLM common subset, N=44 and N=49 v2.0
Coverage0.48
4
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