RTLLM
Benchmarks
| Task Name | Dataset Name | SOTA Result | Trend | |
|---|---|---|---|---|
| Verilog Code Generation | RTLLM v1.1 | Syn@5100 | 31 | |
| Verilog Code Generation | RTLLM v2.0 | Pass@584.09 | 17 | |
| Verilog Code Generation | RTLLM v1 | Pass@172.9 | 16 | |
| RTL code generation | Rtllm (test) | Pass@142 | 16 | |
| RTL generation | RTLLM 50 cases (test) | Pass@10.42 | 16 | |
| RTL code generation | RTLLM v2.0 (test) | Syntax Pass@176.2 | 16 | |
| RTL Design Generation | RTLLM v2.0 | Delay (ns)0.07 | 15 | |
| Verilog Code Generation | RTLLM v2 | Pass@168 | 13 | |
| Verilog Generation | RTLLM v2 | Pass@20090 | 12 | |
| Verilog Generation | RTLLM v2 (test) | Pass@168 | 11 |
Showing 10 of 10 rows