VerilogMachine
Benchmarks
| Task Name | Dataset Name | SOTA Result | Trend | |
|---|---|---|---|---|
| RTL Design Code Generation | VerilogMachine v1 | Syntax Accuracy96.5 | 9 |
Showing 1 of 1 rows
| Task Name | Dataset Name | SOTA Result | Trend | |
|---|---|---|---|---|
| RTL Design Code Generation | VerilogMachine v1 | Syntax Accuracy96.5 | 9 |