DAMO: Deep Agile Mask Optimization for Full Chip Scale
About
Continuous scaling of the VLSI system leaves a great challenge on manufacturing and optical proximity correction (OPC) is widely applied in conventional design flow for manufacturability optimization. Traditional techniques conducted OPC by leveraging a lithography model and suffered from prohibitive computational overhead, and mostly focused on optimizing a single clip without addressing how to tackle the full chip. In this paper, we present DAMO, a high performance and scalable deep learning-enabled OPC system for full chip scale. It is an end-to-end mask optimization paradigm which contains a Deep Lithography Simulator (DLS) for lithography modeling and a Deep Mask Generator (DMG) for mask pattern generation. Moreover, a novel layout splitting algorithm customized for DAMO is proposed to handle the full chip OPC problem. Extensive experiments show that DAMO outperforms the state-of-the-art OPC solutions in both academia and industrial commercial toolkit.
Related benchmarks
| Task | Dataset | Result | Rank | |
|---|---|---|---|---|
| Inverse Lithography | ICCAD 2013 (Avg) | EPE11 | 17 | |
| Inverse Lithography Technology | LithoBench MetalSet Metal Layer | L2 Error3.26e+4 | 12 | |
| Inverse Lithography Technology | LithoBench StdMetal Metal Layer In-distribution | L2 Error1.61e+4 | 12 | |
| Inverse Lithography Technology | LithoBench ViaSet Via Layer | L2 Error5.08e+3 | 11 | |
| Inverse Lithography Technology | LithoBench StdContact (Via Layer, OOD) | L2 Error (Via Layer OOD)5.04e+4 | 11 | |
| Mask Optimization | ICCAD contest benchmark 2013 (test) | L2 Error3.37e+4 | 10 | |
| Mask Generation (OPC) | GAN-OPC synthetic 32 nm M1 (test) | L2 Distance8.47e+3 | 5 | |
| Mask Generation (OPC) | LithoBench MetalSet 32 nm metal-layer ILT (test) | L2 Error3.37e+4 | 5 | |
| Mask Generation (OPC) | LithoBench ViaSet 45 nm via-layer ILT (test) | L2 Error5.98e+3 | 5 | |
| Mask Generation (OPC) | MaskOpt ILT 45 nm metal-layer (test) | L2 Error5.90e+4 | 5 |