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Verilog Code Generation on RTLLM v1.1

100Syn@5

Direct

61.10471.20281.391.398Jul 7, 2025Aug 18, 2025Sep 29, 2025Nov 11, 2025Dec 23, 2025Feb 3, 2026Mar 18, 2026
Updated 6d ago

Evaluation Results

MethodLinks
2026.03
100--
2026.03
10072.4-
2026.03
10089.7-
2026.03
96.682.8-
2025.07
96.6-87.2
2026.03
93.952.9-
2026.03
93.965.8-
2026.03
93.965.5-
2025.07
93.9-65.5
2025.07
93.9-52.9
2025.07
93.9-65.8
2025.07
93.1-72.4
2025.07
93.1-82.8
2025.07
93.1-72.4
2026.03
92.958.8-
2025.07
92.9-58.8
2025.07
89.7-75.8
2026.03
89.553.3-
2025.07
89.5-53.3
2026.03
89.250.3-
2025.07
89.2-50.3
2026.03
87.451.5-
2025.07
87.4-51.5
2025.07
86.2-48.3
2026.03
83.940.3-
2025.07
83.9-40.3
2026.03
73.737.3-
2025.07
73.7-37.3
2025.07
65.8-34
2025.07
64.4-29.3
2025.07
62.6-29.9
2026.03
-65.5-
2025.07
--65.5
2025.07
--62.2